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STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
PRODUCT PREVIEW
1.0 DESCRIPTION
The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer interface for 10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MAC) and a physical media interface for 100BASETX of IEEE802.3u and 10BASE-T of IEEE802.3. The STEPHY1 supports both half-duplex and full-duplex operation, at 10 and 100 Mbps operation. Its operating mode can be set using auto-negotiation, parallel detection or manual control. It also allows for the support of auto-negotiation functions for speed and duplex detection.
PQFP64 ORDERING NUMBER: STE100P
n n
2.0 FEATURE 2.1 Industry standard
n n n
Support for IEEE802.3x flow control IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX MII interface Standard CSMA/CD or full duplex operation supported
IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant
Figure 1. BLOCK DIAGRAM
LEDS
LEDS
100Mb/s
TX_CLK TXD[3:0] TX_ER TX_EN Serial Management 4B/5B
TX Channel
Scrambler Parallel to Serial NRZ To NRZI Encoder
Binary To MLT3 Encoder TRANSMITTER 10/100 10 TX Filter
TXP TXN
10Mb/s
NRZ ToManchester Encoder
Link Pulse Generator
MDIO
Interface / Controller
MDC
REGISTERS
Auto Negotiation
Loopback
Clock Generation
System Clock
RXD[3:0] RX_ER RX_DV RX_CLK
MII
RX Channel 100Mb/s
4B/5B
Descrambler Code Align
Binary ToMLT3 Decoder
Adaptive Equalization BaseLine Wander
Serial to Parallel
NRZI To NRZ Decoder
Clock Recovery
RECEIVER 10/100
RXP RXN
HW configuration pins
10Mb/s
HW Config Power Down
NRZ To Manchester Encoder
Link Pulse Detector
10 TX Filter Clock Recovery
SMART Squelch
January 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STE100P
2.2 Physical Layer
n n n n n n n n n
Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T Provides Full-duplex operation on both 100Mbps and 10Mbps modes Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps Provides MLT-3 transceiver with DC restoration for Base-line wander compensation Provides transmit wave-shaper, receive filters, and adaptive equalizer Provides loop-back modes for diagnostic Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder Supports external transmit transformer with turn ratio 1:1 Supports external receive transformer with turn ratio 1:1
2.3 LED Display
n
Provides 2 kinds of LED display mode: * First mode - 3 LED displays for 100Mbps(on) or 10Mbps(off) Link(Keeps on when link ok) or Activity(Blink with 10Hz when receiving or transmitting but not collision) FD(Keeps on when in Full duplex mode) or Collision(Blink with 20Hz when colliding) * Second mode - 4 LED displays for 100 Link(On when 100M link ok) 10 Link(On when 10M link ok) Activity (Blink with 10Hz when receiving or transmitting) FD(Keeps on when in Full duplex mode) or Collision(Blink with 20Hz when colliding)
2.4 Miscellaneous
n
Standard 64-pin QFP package pinout
Figure 2. System Diagram of the STE100P Application
Serial EEPROM
LEDs
PCI Interface
MAC Device
STE100P
STEPHY1
Transformer
RJ-45
Boot ROM
25 MHz Crystal
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STE100P
3.0 PIN ASSIGNMENT DIAGRAM Figure 3. Pin Connection4. Pin Description
TDS/MDIR RX_ER/RXD TX_ER/TXD
VCCE/I
CFG0
CFG1
CRS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 MF4 MF3 F2 MF1 MF0 FDE GNDE/I GNDA VCCA GNDA X2 X1 VCCA GNDA IREF VCCA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RIP N.C. N.C. RXN RXP TXN VCCA VCCA GNDA GNDA GNDE TEST VRDWN RESET N.C. TXP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RX_DV RXD0 RXD1 VCCE/I RDX2 RDX3 MDC MDIO GNDE VCCE IEDR10 IEDTR IEDL IEDC IEDS SCAN_EN
RX_CLK
D99TL457
TX_CLK
4.0 PIN DESCRIPTION Table 1. Pin Description
Pin No. Name Type Description
MII Data Interface 59 58 57 56 55 54 53 TXD4 TXD3 TXD2 TXD1 TXD0 TX-EN TX-CLK I Transmit Data. The Media Access Controller (MAC) drives data to the STE100P using these inputs. TXD4 is monitored only in Symbol (5B) Mode. These signals must be synchronized to the TX-CLK. Transmit Enable. Thc MAC asserts this signal when it drives valid data on the TXD inputs. This signal must be synchronized to the TX-CLK. Transmit Clock. Normally the STE100P drives TX-CLK. Refer to the Clock Requirements discussion in the Functional Description section. 25 MHz for 100 Mbps operation. 2.5 MHz for 10 Mbps operation. Transmit Coding Error. The MAC asserts this input when an error has occurred in the transmit data stream. When the STE100P is operating at 100 Mbps, the STE100P responds by sending invalid code symbols on the line. . In Symbol (5B) Mode this pin is also equivalent to TXD4.
I I/O
52
TX-ER
I
GNDE/I
TX_EN
TXD3
TXD2
TXD1
TXD0
COL
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STE100P
Table 1. Pin Description
Pin No. 42 43 44 46 47 48 51 Name RXD4 RXD3 RXD2 RXD1 RXD0 RX-DV RX-ER Type O Description Receive Data. Thc STE100P drives received data on these outputs, synchronous to RX-CLK. RXD4 is driven only in Symbol (5B) Mode.
O O
Receive Data Valid. Thc STE100P asserts This signal when it drives valid data on RXD. This output is synchronous to RX-CLK. Receive Error. The STE100P asserts this output when it receives invalid symbols from the network. This signal is synchronous to RX-CLK. In Symbol (5B) Mode this pin is also equivalent to RXD4. Receive Clock. This continuous clock provides reference for RXD. RXDV, and RXER signals. Refer to the Clock Requirements discussion in the Functional Description section. 25 MHz for 100 Mbps operation. 2.5 MHz for 10 Mbps operation. Collision Detected. The STE100P asserts this output when detecting a collision. This output remains High for the duration of the collision. This signal is asynchronous and inactive during full-duplex operation. Carrier Sense. During half-duplex operation (PR0:8=0), the STE100P asserts this output when either transmit or receive medium is non idle. During full duplex operation (PR0:8=1), CRS is asserted only when the receive medium is non-idle.
49
RX-CLK
O
60
COL
O
61
CRS
O
MII Control Interface 41 40 62 MDC MDIO MDINT I I/O OD Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 2.5 MHz. Management Data Input/Output, Bi-directional serial data channel for PHY communication. Management Data Interrupt. When any bit in PR18 = 1, an active Low output on this pin indicates status change in the corresponding bits in PR17. Interrupt is cleared by reading Register PR17
Physical (Twisted Pair) Interface 12 OSC1 I 25 MHz reference clock input. When an external 25 MHz crystal is used, this pin will be connected to one terminal of it. If an external 25 MHz clock source of oscillator is used, then this pin will be the input pin of it. 25 MHz reference clock output. When an external 25MHz crystal is used, this pin will be connected to another terminal of if. If an external clock source is used, then this pin should be left open. The differential Transmit outputs of 100BASE-TX or 10BASE-T, these pins directly output to the transformer. The differential Receive inputs of 100BASE-TX or 10BASE-T, these pins directly input from the transformer. Reference Resistor connecting pin for reference current, directly connects a 5K 1% resistor to Vss.
11
OSC2
O
21 23 19 18 15
TXP TXN RXP RXN Iref
O I O
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STE100P
Table 1. Pin Description
Pin No. 37-33 Name LED/PAD Pins Type I/O Description Pins 33-37 are multifunction pins used as LED outputs and PHY Address sensing inputs for multiple PHY applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 k) to this pin as required. The active state of each LED output driver is dependent on the logic level sampled by the corresponding PHY address input upon power-up/reset. If a given PAD input is resistively pulled low, the corresponding LED output will be configured as an active high driver. Conversely, if a given PAD input is resistively pulled high then the corresponding LED output will be configured as an active low driver. These outputs are standard CMOS voltage drivers and not open-drain. LED display for 10Ms/s link status. This pin will be driven on continually when 10Mb/s network operating speed is detected. The pull-up/pull-down status of this pin is latched into the PR20 bit 7 during power up/reset. LED display for Tx/Rx Activity status. This pin will be driven on with 10 Hz blinking frequency when either effective receiving or transmitting is detected. The status of this pin is latched into the PR20 bit 6 during power up/reset. I/O LED display for Link Status. This pin will be driven on continually when a good Link test is detected. The status of this pin is latched into the PR20 bit 5 during power up/reset. LED display for Full Duplex or Collision status. This pin will be driven on continually when a full duplex configuration is detected. This pin will be driven on with 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. The status of this pin is latched into the PR20 bit 4 during power up/reset. LED display for 100Ms/s link status. This pin will be driven on continually when 100Mb/s network operating speed is detected. The status of this pin is latched into the PR20 bit 3 during power up/reset. Configuration Control 0. When A/N is enabled, CFG0 determines operating mode advertisement capabilities in combination with CFG1 when MF0/ PR0:12 =1. (See Table 2) When A/N is disabled, CFG1 disables MLT3 and directly affects PR19:0 When CFG0 is Low, MLT3 encoder/decoder is enabled and PR19:1 =0. When CFG0 is High, MLT3 encoder/decoder is bypassed and PR19:1 = 1. Configuration Control 1. When A/N is enabled, CFG1 determines operating mode advertisement capabilities in combination with CFG1 when MF0/ PR0:12 =1. (See Table 2) When A/N is disabled, CFG1 enables Loopback mode and directly affects PR0 bit 14. When CFG1 is Low, Loopback mode is disabled and PR0:14 = 0. When CFG1 is High, Loopback mode is enabled and PR0:14 = 1. Description Reset (Active-Low). This input must be held low for a minimum of 1 ms to reset the STE100P. During Power-up, the STE100P will be reset regardless of the state of this pin, and this reset will not be complete until after >1ms. Reset In Progress. This output is used to indicate when the device has completed power-up/reset and the registers and functions can be accessed. When RIP is High, power-up/reset has been successful and the device can be used normally When RIP is Low, device reset is not complete.
37
LED10/ PAD[4]
I/O
36
LEDTR/ PAD[3] LEDL /PAD[2] LEDC / PAD[1]
35
34
I/O
33
LEDS / PAD[0] CFG0
I/O
31
I
32
CFG1
I
Pin No. 29
Name RESET
Type I
63
RIP
O
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STE100P
Table 1. Pin Description
Pin No. 30 Name PWRDWN Type I Description Power Down. When High, forces STE100P into Power Down mode. This pin is OR'ed with the Power Down bit (PR0:11). During the Power Down mode, TXP/ TXN outputs and all LED outputs are 3-stated, and the MII interface is isolated. Multi-Function pins. Each MF pin internally drives different configuration functions. The functions of the five MF inputs are as follows: Pin MF0 MF1 MF2 MF3 mf4 Function Auto-Negotiation Enable NRZ-NRZI conversion 4B/5B Coding Enable Scrambler Operation Disable MF4 10/100 Mbps Speed Select Register & Bit Affected PR0:12 ANE PR19:7 ENRZI PR19:6 EN4B5B PR19:0 DISCRM PR0:13 SPSEL
5 4 3 2 1
MF0 MF1 MF2 MF3 MF4
I
The logic level of MF0-4 will determine the value that the affected bits will have upon reset of the STE100P. The operating functions of CFG0, CFG1, and FDE change depending on the state of MF0 (Auto-Negotiation enabled or disabled). Table 2 shows the relationship between CFG0, CFG1 and FDE . 6 FDE I Full-Duplex Enable. When A/N is enabled, FDE determines full-duplex advertisement capability in combination with CFG0 and CFG1. (See Table 2) When A/N is disabled, FDE directly affects full-duplex operation and determines the value of PR0 bit 8 (Full/Half Duplex Mode Select). When FDE is High, full-duplex is enabled and PR0:8 = 1. When FDE is Low, full-duplex is disabled and PR0:8 = 0.
Digital Power Pins 38, 45, 64 7, 25, 39, 50 Analog Power Pins 9, 13, 16, 17, 22 8, 10, 14, 20, 24 VCCA GNDA VCCE, VCCE/I GNDE, GNDE/I
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STE100P
5.0 HARDWARE CONTROL INTERFACE 5.1 Operating Configurations
The Hardware Control Interface consists of the MF<4:0>, CFG <1:0> and FDE input pins as well as the LED/ PAD pins. This interface is used to configure operating characteristics of the STE100P. The Hardware Control Interface provides initial values for the MDIO registers, and then passes control to the MDIO Interface. Individual chip addressing via the LED/PAD pins allows multiple STE100P devices to share the MII interface. Table 2 shows how to set up the desired operating configurations using the Hardware Control Interface.
Table 2. Operating Configurations / Auto-Negotiation Enabled
Desired Configuration Advertise All Advertise 100 HD Advertise 100 HD/FD Advertise 10 HD Advertise 10 HD/FD Advertise 10/100 HD Input Value CFG0 1 1 1 0 0 1 CFG1 1 0 0 1 1 1 FDE 1 0 1 0 1 0 [8] TXF 1 0 1 0 0 0 PR4 Register Bits Affected [7] TXH 1 1 1 0 0 1 [6] 10F 1 0 0 0 1 0 [5] 10H 1 0 0 1 1 1
Note: If pin 5, MF0 = 0, or ANE (pin MF0 / PR0:12) = 0 (Auto-Negotiation disabled), then PR4 bits 5-8 will contain the default value indicated in the table describing register PR4.
5.2 LED / PHY Address Interface
The LED output pins can be used to drive LED's directly, or can be used to provide status information to a network management device. The active state of each LED output driver is dependent on the logic level sampled by the corresponding PHY address input upon power-up/reset. For example, if a given PAD input is resistively pulled low then the corresponding LED output will be configured as an active high driver. Conversely, if a given PAD input is resistively pulled high then the corresponding LED output will be configured as an active low driver. These outputs are standard CMOS drivers and not open-drain. The STE100P PAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros (00000) will result in a PHY isolation condition as a result of power-on/reset, as documented for PR0 bit 11. See Section 7 for more detailed descriptions of device operation.
6.0 REGISTERS AND DESCRIPTORS DESCRIPTION
There are 11 registers with 16 bits each supported for STE100P. This includes 7 basic registers which are defined according to the clause 22 "Reconciliation Sub-layer and Media Independent Interface" and clause 28 "Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair" of IEEE802.3u standard. There are 11 registers with 16 bits each supported for the STE100P. These include 7 basic registers which are defined according to the clause 22 "Reconciliation Sublayer and Media Independent Interface" and clause 28 "Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair" of IEEE802.3u standard. In addition, there are 4 special registers for advanced chip control and status information.
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STE100P
6.1 Register List Table 3. Register List
Address 0 1 2 3 4 5 6 17 18 19 20 Reg. Index PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR17 PR18 PR19 PR20 Name XCR XSR PID1 PID2 ANA ANLPA ANE XCIIS XIE 100CTR XMC Register Descriptions XCVR Control Register XCVR Status Register PHY Identifier 1 PHY Identifier 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register XCVR Configuration Information and Interrupt Status Register XCVR Interrupt Enable Register 100BASE-TX PHY Control/Status Register XCVR Mode Control Register
6.2 Register Descriptions Table 4. Register Descriptions
Bit # Name Descriptions Default Val RW Type
PR0- XCR, XCVR Control Register. The default values on power-up/reset are as listed below. 15 XRST Reset control. 1: Device will be reset. This bit will be cleared by STE100P itself after the reset is completed. Loop-back mode select. 1: Loop-back mode is selected. Network Speed select. This bit's selection will be ignored if Auto-Negotiation is enabled(bit 12 of PR0 = 1). 1:100Mbps is selected. 0:10Mbps is selected. Auto-Negotiation ability control. 1: Auto-Negotiation function is enabled. 0: Auto-Negotiation is disabled. Power-down mode control. 1: Power-down mode is selected. Setting this bit puts the STE100P into power-down mode. During the power-down mode, TXP/TXN and all LED outputs are 3-stated, and the MII interface is isolated. 0 R/W
14 13
XLBEN SPSEL
0 1
R/W R/W
12
ANEN
1
R/W
11
PDEN
0
R/W
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STE100P
Table 4. Register Descriptions
Bit # 10 Name ISOEN Descriptions 0 - Normal operation. 1 - Isolate PHY from MII. Setting this control bit isolates the STE100P from the MII, with the exception of the serial management inter-face. When this bit is asserted, the STE100Pdoes not respond to TXD[3:0], TX-EN, and TX-ER inputs, and it presents a high impedance on its TX-CLK, RX-CLK, RX-DV, RX-ER, D[3:0], COL, and CRS outputs. This bit is initialized to 0 unless the configuration pins for the PHY address are set to 00000h during power-up or reset. Re-Start Auto-Negotiation process control. 1: Auto-Negotiation process will be re-started. This bit will be cleared by STE100P itself after the Auto-negotiation restarted. Full/Half duplex mode select. 1: full duplex mode is selected. This bit will be ignored if AutoNegotiation is enabled (bit 12 of PR0 = 1). Collision test control. 1: collision test is enabled. 0: normal operation This bit, when set, causes the COL signal to be asserted as a result of the assertion of TX _EN within 512 BT. De-assertion of TX_EN will cause the COL signal to be de-asserted within 4BT. Reserved Default Val 0 RW Type R/W
9
RSAN
0
R/W
8
DPSEL
0
R/W
7
COLEN
0
R/W
6~0
---
0
RO
R/W = Read/Write able. RO = Read Only.
PR1- XSR, XCVR Status Register. All the bits of this register are read only. 15 14 13 12 11 10~7 6 T4 TXFD TXHD 10FD 10HD --MFPS 100BASE-T4 ability. Always 0, since STE100P has no T4 ability. 100BASE-TX full duplex ability. Always 1, since STE100P has the 100BASE-TX full duplex ability. 100BASE-TX half duplex ability. Always 1, since STE100P has the 100BASE-TX half duplex ability. 10BASE-T full duplex ability. Always 1, since STE100P has 10Base-T full duplex ability. 10BASE-T half duplex ability. Always 1, since STE100P has 10Base-T half duplex ability. Reserved MF Preamble Suppression 1 =Accepts management frames with pre-amble suppressed. 0 = Will not accept management frames with preamble suppressed. The value of this bit is controlled by bit 1 of PR20. Its default of 1 indicates that the SFEPHY1 accepts management frame without preamble. A minimum of 32 preamble bits are required following power-on or hardware reset. One IDLE bit is required between any two management transactions as per IEEE 802.3u specification. 0 1 1 1 1 0 1 RO RO RO RO RO RO RO
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STE100P
Table 4. Register Descriptions
Bit # 5 Name ANC Descriptions Auto-Negotiation Completed. 0: Auto-Negotiation process is not completed . 1: Auto-Negotiation process is completed. Result of remote fault detection. 0: No remote fault condition detected. 1: Remote fault condition detected. This bit is set when the Link Partner transmits a remote fault condition (PR5 bit 13 = 1). Auto-Negotiation ability. Always 1, since STE100P has the Auto-Negotiation ability. Link status. 0: a failure link condition occurred. Read to set. 1: a valid link is established. Jabber detection. 1: jabber condition is detected (10Base-T only). Extended register supporting. Always 1, since STE100P supports extended register Default Val 0 RW Type RO
4
RF
0
RO/LH*
3 2
AN LINK
1 0
RO RO/LL*
1 0
JAB EXT
0 1
RO/LH* RO
LL* = Latching Low and clear by read. LH* = Latching High and clear by read.
PR2- PID1, PHY Identifier 1 15~0 PHYID1 Part one of PHY Identifier. Assigned to the 3rd to 18th bits of the Organizationally Unique Identifier (OUI). (The ST OUI is 0080E1 hex). 1C04h RO
PR3- PID2, PHY Identifier 2 15~10 PHYID2 Part two of PHY Identifier. Assigned to the 19th to 24th bits of the Organizationally Unique Identifier (OUI). Model number of STE100P. Six bits manufacture's model number. Revision number of STE100P. Four bits manufacture's revision number. 000000b RO
9~4 3~0
MODEL REV
000001b 0001b
RO RO
PR4- ANA, Auto-Negotiation Advertisement 15 14 13 12,11 10 9 NXTPG --RF --FC T4 Next Page ability. Always 0: since STE100P does not provide next page ability. Reserved Remote Fault function. 1: with remote fault function. Reserved Flow Control function Ability. 1:supports PAUSE operation of flow control for full duplex link. 100BASE-T4 Ability. Always 0: since STE100P doesn't have 100BASE-T4 ability. 1 0 R/W RO 0 R/W 0 RO
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STE100P
Table 4. Register Descriptions
Bit # 8 7 6 5 4~0 Name TXF TXH 10F 10H SF Descriptions 100BASE-TX Full duplex Ability. 1: with 100Base-TX full duplex ability. 100BASE-TX Half duplex Ability. 1: with 100Base-TX ability. 10BASE-T Full duplex Ability. 1: with 10Base-T full duplex ability. 10BASE-T Half duplex Ability. 1: with 10Base-T ability. Select field. Default 00001=IEEE 802.3 Default Val 1 1 1 1 00001 RW Type R/W R/W R/W R/W RO
PR5- ANLP, Auto-Negotiation Link Partner ability 15 LPNP Link partner Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability. Received Link Partner Acknowledge. 0: link code work had not received yet. 1: link partner successfully received STE100P's Link Code Word. Link Partner's Remote fault status. 0: no remote fault detected. 1: remote fault detected. Reserved Link Partner's Flow control ability. 0: link partner without PAUSE function ability. 1: link partner with PAUSE function full duplex link ability. Link Partner's 100BASE-T4 ability. 0: link partner without 100BASE-T4 ability. 1: link partner with 100BASE-T4 ability. Link Partner's 100BASE-TX Full duplex ability. 0: link partner without 100BASE-TX full duplex ability. 1: link partner with 100BASE-TX full duplex ability. Link Partner's 100BASE-TX Half duplex ability. 0: link partner without 100BASE-TX. 1: link partner with 100BASE-TX ability. Link Partner's 10BASE-T Full Duplex ability. 0: link partner without 10BASE-T full duplex ability. 1: link partner with 10BASE-T full duplex ability. Link Partner's 10BASE-T Half Duplex ability. 0: link partner without 10BASE-T ability. 1: link partner with 10BASE-T ability. Link partner select field. Default 00001=IEEE 802.3. 0 RO
14
LPACK
0
RO
13
LPRF
0
RO
12,11 10
--LPFC
0 0
RO RO
9
LPT4
0
RO
8
LPTXF
0
RO
7
LPTXH
0
RO
6
LP10F
0
RO
5
LP10H
0
RO
4~0
LPSF
00001
RO
PR6- ANE, Auto-Negotiation expansion 15~5 --Reserved 0 RO
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STE100P
Table 4. Register Descriptions
Bit # 4 Name PDF Descriptions Parallel detection fault. 0: no fault detected. 1: a fault detected via parallel detection function. Link Partner's Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability. STE100P's next Page ability. Always 0, since STE100P without next page ability. Page Received. 0: no new page has been received. 1: a new page has been received. Link Partner Auto-Negotiation ability. 0: link partner has no Auto-Negotiation ability. 1: link partner has Auto-Negotiation ability. Default Val 0 RW Type RO/LH*
3
LPNP
0
RO
2 1
NP PR
0 0
RO RO/LH*
0
LPAN
0
RO
LH = High Latching and cleared by reading.
PR17- XCIIS, XCVR Configu ration information and Interrupt Status
15~10
9
---SPEED
Reserved Configured information of Speed. 0: the speed is 10Mb/s. 1: the speed is 100Mb/s. Configured information of Duplex. 0: the duplex mode is half. 1: the duplex mode is full. Configured information of PAUSE function for flow control. 0: PAUSE function is disabled. 1: PAUSE function is enabled Interrupt source of Auto-Negotiation Completed. 0: Auto-Negotiation has not completed yet. 1: Auto-Negotiation has completed. Interrupt source of Remote Fault Detected. 0: there is no remote fault detected. 1: remote fault is detected. Interrupt source of Link Fail. 0: link test status is up. 1: link is down. Interrupt source of Auto-Negotiation Acknowledge Received. 0: there is no link code word received. 1: link code word is receive from link partner. Interrupt source of Parallel Detection Fault. 0: there is no parallel detection fault. 1: parallel detection is fault. Interrupt source of Auto-Negotiation Page Received. 0: there is no Auto-Negotiation page received. 1: auto-negotiation page is received.
0 0
RO RO
8
DUPLEX
0
RO
7
PAUSE
0
RO
6
ANC
0
RO/LH*
5
RFD
0
RO/LH*
4
LS
0
RO/LH*
3
ANAR
0
RO/LH*
2
PDF
0
RO/LH*
1
ANPR
0
RO/LH*
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STE100P
Table 4. Register Descriptions
Bit # 0 Name REF Descriptions Interrupt source of Receive Error full. 0: the receive error number is less than 64. 1: 64 error packets are received. Default Val 0 RW Type RO/LH*
LH = High Latching and cleared by reading.
PR18- XIE, XCVR Interrupt Enable Register 15~7 6 --ANCE Reserved Auto-Negotiation Completed interrupt Enable. 0: disable Auto-Negotiation completed interrupt. 1: enable Auto-Negotiation complete interrupt. Remote Fault detected interrupt Enable. 0: disable remote fault detection interrupt. 1: enable remote fault detection interrupt. Link Down interrupt Enable. 0: disable link fail interrupt. 1: enable link fail interrupt. Auto-Negotiation Acknowledge interrupt Enable. 0: disable link partner acknowledge interrupt 1: enable link partner acknowledge interrupt. Parallel Detection Fault interrupt Enable. 0: disable fault parallel detection interrupt. 1: enable fault parallel detection interrupt. Auto-Negotiation Page Received interrupt Enable. 0: disable Auto-Negotiation page received interrupt. 1: enable Auto-Negotiation page received interrupt. RX_ERR full interrupt Enable. 0: disable rx_err full interrupt. 1: enable more than 64 time rx_err interrupt, 0 R/W
5
RFE
0
R/W
4
LDE
0
R/W
3
ANAE
0
R/W
2
PDFE
0
R/W
1
ANPE
0
R/W
0
REFE
0
R/W
PR19- 100CTR, 100BASE-TX Control Register 15,14 13 --DISRER reserved Disable the RX_ERR counter. 0: the receive error counter - RX_ERR is enabled. 1: the receive error counter - RX_ERR is disabled. Auto-Negotiation completed. This bit is the same as PR1:5. 0: the Auto-Negotiation process has not completed yet. 1: the Auto-Negotiation process has completed. Select peak to peak voltage of receive. 0: receive voltage peak to peak 1.0 VPP 1: receive voltage peak to peak 1.4 VPP. reserved Enable remote loop-back function. 1: enable Enable DC restoration. 0: disable DC restoration. 1: enable DC restoration. 0: disable 0 1 R/W R/W 0 R/W
12
ANC
0
RO
11
RXVPP
0
R/W
10 9 8
--ENRLB ENDCR
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STE100P
Table 4. Register Descriptions
Bit # 7 Name ENRZI Descriptions Enable the conversions between NRZ and NRZI. 0: disable the data conversion between NRZ and NRZI. 1: enable the data conversion of NRZI to NRZ in receiving and NRZ to NRZI in transmitting. Enable 4B/5B encoder and decoder 0: the 4B/5B encoder and decoder are bypassed 1: the 4B/5B encoder and decoder are enabled.. Transmit Isolation. When 1, isolate from MII and tx+/-. The bit will be set to one if the PHY address is set to 00000 at powerup/reset This bit must be 0 for normal operation Reporting of current operation mode of transceiver. 000: in auto-negotiation 001: 10Base-T half duplex 010: 100Base-TX half duplex 011: reserved 100: reserved 101: 10Base-T full duplex 110: 100Base-TX full duplex 111: isolation, auto-negotiation disable Disable MLT3. 0: the MLT3 encoder and decoder are enabled. 1: the MLT3 encoder and decoder are bypassed. Disable Scramble. 0: the scrambler and de-scrambler is enabled. 1: the scrambler and de-scrambler are disabled. Default Val 1 RW Type R/W
6
EN4B5B
1
R/W
5
ISOTX
0
R/W
4~2
CMODE
000
RO
1
DISMLT
0
R/W
0
DISCRM
0
R/W
PR20- XMC, XCVR Mode control 15~12 11 --LD Reserved Long Distance mode of 10BASE-T. 0: normal squelch level. 1: reduces 10Base-T squelch level for extended cable length. As the length of the cable increases, so does the current. Reserved PHY Address [4:0]: The values of the PAD[4:0] pins are latched to this register at power-up/reset. The first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY. A PHY address of <00000> that is latched in to the part at power-up/reset will cause the Isolate bit of the PR0 (bit 10, register address 00h) to be set. After power up/reset the only way to enable or disable isolate mode is to set or clear the Isolate bit (bit 10) PR0. After power up/reset writing <00000> to bits [4:0] of this register will not cause the part to enter isolate mode. reserved 0 0 RO R/W
10~8 7~3
--PAD4:0
0 [00001]
RO Strap, R/W
2
---
0
RO
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STE100P
Table 4. Register Descriptions
Bit # 1 Name MFPSE Descriptions MF Preamble Suppression Enable 1 = Accept management frames with pre-amble suppressed. 0 = Do not accept management frames with preamble suppressed. This bit also controls the value of bit 6 in PR1 (MFPS). reserved Default Val 1 RW Type R/W
0
---
0
RO
7.0 DEVICE OPERATION
The STE100P integrates the IEEE802.3u compliant functions of PCS(physical coding sub-layer), PMA(physical medium attachment) sub-layer, and PMD(physical medium dependent) sub-layer for 100BASE-TX, and the IEEE802.3 compliant functions of Manchester encoding/decoding and transceiver for 10BASE-T. All the functions and operation schemes are described in the following sections.
7.1 100BASE-TX Transmit Operation
Regarding the 100BASE-TX transmission, the device provides the transmission functions of PCS, PMA, and PMD for encoding of MII data nibbles to five-bit code-groups (4B/5B), scrambling, serialization of scrambled code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and then driving the MLT3 code into the category 5 Unshielded Twisted Pair cable through an isolation transformer with the turns ratio of 1.414 : 1.
Data code-groups Encoder: In normal MII mode application, the device receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the device on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100BASE-TX. Idle code-groups: In order to establish and maintain the clock synchronization, the device needs to keep transmitting signals to the medium. The device will generate Idle code-groups for transmission when there is no real data want to be sent by MAC. Start-of-Stream Delimiter-SSD (/J/K/): In a transmission stream, the first 16 nibbles are MAC preamble. In order to let partner delineate the boundary of a data transmission sequence and to authenticate carrier events, the devicewill replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups. End-of-Stream Delimiter-ESD (/T/R/): In order to indicate the termination of the normal data transmissions, the device will insert 2 nibbles of /T/R/ code-group after the last nibble of FCS. Scrambling: All the encoded data(including the idle, SSD, and ESD code-groups) is passed to the data scrambler to reduce the EMI and spread the power spectrum using a 10-bit scrambler seed loaded at the beginning. Data conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3: After scrambled, the transmission data with 5B type in 25MHz will be converted to serial bit stream in 125MHz by the parallel to serial function. After serialized, the transmission serial bit stream will be further converted from NRZ to NRZI format. This NRZI conversion function can be bypassed, if the bit 7 of PR19 register is cleared as 0. After NRZI converted, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3 code. With this MLT3 code, it lowers the frequency and reduces the energy of the transmission signal in the UTP cable and also makes the system easily to meet the FCC specification of EMI. Wave-Shaper and Media Signal Driver: In order to reduce the energy of the harmonic frequency of transmission signals, the device provides the wave-shaper prior tothe line driver to smooth but keep symmetric the rising/falling edge of transmission signals. The wave-shaped signals include the 100BASE-TX and 10BASE-T both are passed to the same media signal driver. This design can simplify the external magnetic connection with single one.
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STE100P
7.2 100BASE-TX Receiving Operation
Regarding the 100BASE-TX receiving operation, the device provides the receiving functions of PMD, PMA, and PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with turns ratio of 1: 1. It includes the adaptive equalizer and baseline wander, data conversions of MLT3 to NRZI, NRZI to NRZ and serial to parallel, the PLL for clock and data recovery, the de-scrambler, and the decoder of 5B/4B.
Adaptive Equalizer and Baseline Wander: Since the high speed signals over the unshielded (or shielded) twisted Pair cable will induce the amplitude attenuation and phase shifting. Furthermore, these effects are depends on the signal frequency, cable type, cable length and the connectors of the cabling. So a reliable adaptive equalizer and baseline wander to compensate all the amplitude attenuation and phase shifting are necessary. In the transceiver, it provides the robust circuits to perform these functions. MLT3 to NRZI Decoder and PLL for Data Recovery: After receiving the proper MLT3 signals, the device converts the MLT3 to NRZI code for further processing. After adaptive equalizer, baseline wander, and MLT3 to NRZI decoder, the compensated signals with NRZI type in 125MHz are passed to the Phase Lock Loop circuits to extract out the original data and synchronous clock. Data Conversions of NRZI to NRZ and Serial to Parallel: After data is recovered, the signals will be passed to the NRZI to NRZ converter to generate the 125 MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion can be bypassed, if the bit 7 of PR19 register is cleared as 0. De-scrambling and Decoding of 5B/4B: The parallel 5B type data is passed to de-scrambler and 5B/4B decoder to return their original MII nibble type data. Carrier sensing: Carrier Sense(CRS) signal is asserted when the STE100P detects any 2 non-contiguous zeros within any 10 bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive. But in full duplex mode, CRS is asserted only during packet reception.
7.3 10BASE-T Transmission Operation
This includes the parallel to serial converter, Manchester Encoder, Link test function, Jabber function and the transmit wave-shaper and line driver described in the section of "Wave-Shaper and Media Signal Driver" of "100BASE-T Transmission Operation". It also provides Collision detection and SQE test for half duplex application.
7.4 10BASE-T Receive Operation
This includes the carrier sense function, receiving filter, PLL for clock and data recovering, Manchester decoder, and serial to parallel converter.
7.5 Loop-back Operation
The STE100P provides internal loop-back option for both the 100BASE-TX and 10BASE-T operations. Setting bit 14 of PR0 register to 1 can enable the loop-back option. In this loop-back operation, the TX and RX lines are isolated from the media. The STE100P also provides remote loop-back operation for 100BASE-TX operation. Setting bit 9 of PR19 register to 1 enables the remote loop-back operation. In the 100BASE-TX internal loop-back operation, the data comes from the transmit output of NRZ to NRZI converter then loop-back to the receive path into the input of NRZI to NRZ converter. In the 100BASE-TX remote loop-back operation, the data is received from RX pins through receive path to the output of data and clock recover and then loop-back to the input of NRZI to MLT3 converter of transmit path then transmit out to the medium via the transmit line drivers. In the 10BASE-T loop-back operation, the data is through transmit path and loop-back from the output of the Manchester encoder into the input of Phase Lock Loop circuit of receive path.
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STE100P
7.6 Full Duplex and Half Duplex Operation
The STE100P can operate for either full duplex or half duplex network application. In full duplex, both transmit and receive can be operated simultaneously. Under full duplex mode, collision(COL) signal is ignored and carrier sense(CRS) signal is asserted only when the STE100P is receiving. In half duplex mode, either transmit or receive can be operated at one time. Under half duplex mode, collision signal is asserted when transmit and receive signals collided and carrier sense asserted during transmission and reception.
7.7 Auto-Negotiation Operation
The Auto-Negotiation function is designed to provide the means to exchange information between the STE100P and the network partner to automatically configure both to take maximum advantage of their abilities, and both are setup accordingly. The Auto-Negotiation function can be controlled through ANE, bit 12 of the PR0 register, or the MF0 pin 5. Auto-Negotiation exchanges information with the network partner using the Fast Link Pulses(FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in the burst pulses to advertise all remote partner's capabilities which are determined by the register of PR4. According to this information they find out their highest common capability by following the priority sequence as below: 1. 100BASE-TX full duplex 2. 100BASE-TX half duplex 3. 10BASE-T full duplex 4. 10BASE-T half duplex During power-up or reset, if Auto-Negotiation is found enabled then FLPs will be transmitted and the Auto-Negotiation function will procede. Otherwise, the Auto-Negotiation will not occur until the bit 12 of PR0 register is set to 1. When Auto-Negotiation is disabled, then the Network Speed and Duplex Mode are selected by programming PR0 register.
7.8 Power Down Operation
To reduce the power consumption, the STE100P is designed with a power down feature, which can save the power consumption significantly. Since the power supply of the 100BASE-TX and 10BASE-T circuits are separated, the STE100P can turn off the circuit of either the 100BASE-TX or 10BASE-T when the other one of them is operating. There is also a Power Down mode which can be selected by PDEN in register PR0 bit 11. During the Power Down mode, TXP/TXN outputs and all LED outputs are 3-stated, and the MII interface is isolated. During Power Down mode the MII management interface is still available for reading and writing device registers. Power Down mode can be exited by clearing bit 11 of register PR0 or by a hardware or software reset (setting PR0:15=1).
7.9 LED Display Operation
The STE100P provides 2 functions for the LED pins, the detail descriptions about the operation are described in the PIN Description section, and as follows. * First mode - 3 LED displays for: * 100Mbps (on) or 10Mbps (off) * Link (Stays on when link okay) or Activity (Blinks at 10Hz when receiving or transmitting, but not collision) * FD (Stays on when in Full duplex mode) or Collision (Blinks at 20Hz when a collision occurs) * Second mode - 4 LED displays for: * 100 Link (On when 100M link is okay) * 10 Link (On when 10M link is okay) * Activity (Blinks at 10Hz when receiving or transmitting) * FD (Stays on when in Full duplex mode) or Collision (Blinks at 20Hz when a collision occurs)
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STE100P
7.10 Reset Operation
There are two ways to reset the STE100P. First, for hardware reset, the STE100P can be reset via RESET pin (pin 29). The active low Reset input signal is required at least 1 ms to ensure proper reset operation. Second, for software reset, when bit 15 of register PR0 is set to 1, the STE100P will reset entire circuits and registers to their default values, then clear the bit 15 of PR0 to 0, and set the RIP output pin 63 to logic 1. Both hardware and software reset operations initialize all registers to their default values. This process includes re-evaluation of all hardware-configurable registers. Logic levels on several I/O pins are detected during hardware reset period to determine the initial functionality of STE100P. Some of these pins are used as outputs after the reset operation. Care must be taken to ensure that the configuration setup will not interfere with normal operation. Dedicated configuration pins can be tied to the Vcc or ground directly. Configuration pins multiplexed with LED outputs should be weakly pulled up or weakly pulled down through resistors as shown in the following circuits.
Vcc I/O PIN
10k
10k
I/O PIN
Logic Level 1
Logic Level 0
7.11 Preamble Suppression
Preamble suppression mode in the STEPHY1 is indicated by a one in bit six of the PR1 Register. If it is determined that all PHY devices in the system support preamble suppression, then a preamble is not necessary for each management transaction. The first transaction following power-up/hardware reset requires 32 bits of preamble. The full 32 bit preamble is not required for each additional transaction. The STEPHY1 will respond to management accesses without preamble, but a minimum of one idle bit between management transactions is required as specified in IEEE 802.3u.
7.12 Remote Fault
The remote fault function indicates to a link partner that a fault condition has occurred by using the Remote Fault bit, which is encoded in bit 13 of the Link Code Word. A local device indicates to its link partner that it has found a fault by setting the Remote Fault bit in the Auto-Negotiation register to logic one and renegotiating with the link partner. The Remote Fault bit remains at logic one until successful negotiation with the Link Code Word occurs. The bit will then return to 0. When the message is sent that the Remote Fault bit is set to logic one, the device will set the Remote Fault bit in the MII to logic one if the management function is present.
7.13 Transmit Isolation
STA/STE Ethernet
ttp
STEPHY1
RxD TxD 4/5 4/5 tpn
MII
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TX(100MHz)/TP(10MHz)
STE100P
8.0 ELECTRICAL SPECIFICATIONS AND TIMINGS Table 5. Absolute Maximum Ratings
Parameter Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection -0.5 V to 7.0 V -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -65 C to 150 C(-85F to 302F) 0C to 70C(32F to 158F) 2000V Value
Table 6. General DC Specifications
Symbol General DC Vcc Icc Supply Voltage Power Supply 3.15 3.3 100 3.45 V mA Parameter Test Condition Min. Typ. Max. Units
10BASE-T Voltage/Current Characteristics Rid10 Vida10 Vidr10 Vicm10 Vod10 Icct10 Input Differential Resistance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Input Common Mode Voltage Output Differential Peak Voltage Line Driver Supply 2200 TBD DC 5MHz ~ 10MHz 5MHz ~ 10MHz 585 0 TBD 2800 TBD 3100 585 k mV mV V V mA
100BASE-TX Voltage/Current Characteristics Rid100 Vida100 Vidr100 Input Differential Resistance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage 200 0 TBD 950 TBD 1050 TBD 1000 200 k mV mV V V mA
Vicm100 Input Common Mode Voltage Vod100 Icct100 Output Differential Peak Voltage Line Driver Supply
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STE100P
Table 7. AC Specifications
Symbol X1 Specifications TX1d TX1p TX1t X1 Duty Cycle X1 Period X1 Tolerance 45 50 30 55 % ns PPM Parameter Test Condition Min. Typ. Max. Units
10BASE-T Normal Link Pulse(NLP) Timings Specifications TNPW TNPC NLP Width NLP Period 10Mbps 10Mbps 8 100 24 ns ms
Figure 4. Normal Link Pulse timings
Tnpw
Tnpc
Table 7. AC Specifications
Symbol Parameter Test Condition Min. Typ. Max. Units
Auto-Negotiation Fast Link Pulse(FLP) Timings Specifications Tflpw Tflcpp Tflcpd Tflbw Tflbp FLP Width Clock pulse to clock pulse period Clock pulse to Data pulse period Number of pulses in one burst Burst Width FLP Burst period 8 111 55.5 17 2 16 24 100 125 62.5 139 69.5 33 ns s s pulse ms ms
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STE100P
Figure 5. Fast Link Pulse timing Tflcpp Tflcpd Tflpw
Tflbw
Tflbp
Table 7. AC Specifications
Symbol Parameter Test Condition Min. Typ. Max. Units
100BASE-TX Transmitter AC Timing s Specification Tjit TDP-TDN Differential Output Peak Jitter 1.4 ps
MII Management Clock Timing Specification s t1 t2 t3 t4 t5 t6 MDC Low Pulse Width MDC High Pulse Width MDC Period MDIO(I) Setup to MDC Rising Edge MDIO(O) Hold Time from MDC Rising Edge MDIO(O) Valid from MDC Rising Edge 200 200 400 10 10 0 -- -- -- -- -- 300 ns ns ns ns ns ns
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STE100P
Figure 6. MII Management Clock Timing
t1 MDC t4 MDIO(I) t6 MDIO(O) t5
t2
t3
Table 7. AC Specifications
Symbol Parameter Test Condition Min. Typ. Max. Units
MII Receive Timing Specification t1 t2 t3 RX-ER, RX-DV, RXD[3:0] Setup to RX-CLK RX-ER, RX-DV, RXD[3:0] Hold After RX-CLK RX-CLK High Pulse Width (100 Mbits/s) RX-CLK High Pulse Width (10 Mbits/s) t4 RX-CLK Low Pulse Width (100 Mbits/s) RX-CLK Low Pulse Width (10 Mbits/s) t5 RX-CLK Period (100 Mbits/s) RX-CLK Period (10 Mbits/s) 14 140 40 400 10 10 14 200 26 260 -- -- 26 ns ns ns ns ns ns ns ns
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STE100P
Figure 7. MII Receive Timing
Table 7. AC Specifications
Symbol Parameter Test Condition Min. Typ. Max. Units
MII Transmit Timing Specification t1 t2 TX-ER,TX-EN,TXD[3:0] Setup to TX-CLK Rise TX-ER,TX-EN,TXD[3:0] Hold After TX-CLK Rise 10 0 -- 25 ns ns
Figure 8. MII Transmit Timing
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STE100P
Table 7. AC Specifications
Symbol Parameter Test Condition Min. Typ. Max. Units
Receive Timing Specification Rt1 Receive Frame to Sampled Edge of RX-DV (100 Mbits/s) Receive Frame to Sampled Edge of RX-DV (10 Mbits/s) Rt2 Receive Frame to CRS High (100Mbits/s) Receive Frame to CRS High (10 Mbits/s) Rt3 End of Receive Frame to Sampled Edge of RX-DV (100 Mbits/s) End Receive Frame to Sampled Edge of RX-DV (10 Mbits/s) Rt4 End of Receive Frame to CRS Low (100 Mbits/s) End of Receive Frame to CRS Low (10 Mbits/s) -- 15 bits
--
22
bits
-- -- --
13 5 12
Bits bits bits
-- 13 --
4 24 4.5
bits bits bits
Figure 9. Receive Timing
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STE100P
Table 7. AC Specifications
Symbol Parameter Test Condition Min. Typ. Max. Units
Transmit Timing Specification t1 TX-EN Sampled to CRS High (100 Mbits/s) TX-EN Sampled to CRS High (10 Mbits/s) t2 TX-EN Sampled to CRS Low (100 Mbits/s) TX-EN Sampled to CRS Low (10 Mbits/s) t3 Transmit Latency (100 Mbits/s) Transmit Latency (10 Mbits/s) t4 Sampled TX-EN Inactive to End of Frame (100 Mbits/s) Sampled TX-EN Inactive to End of Frame (10 Mbits/s) 0 -- 0 -- 6 4 -- 4 1.5 16 16 14 -- 17 bits bits bits bits bits bits bits
--
5
bits
Figure 10. Transmit Timing
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STE100P
Figure: 11 Transmit Timing
TXP
Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency)
Sym t2A t2B t2C t2D t2E
Min 10 5 6
Typ 3 4 10
Max 4 16 14
Units ns ns BT BT BT
BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
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STE100P
Figure 12: 10Base-T Transmit Timing
TXP
Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency)
Sym t8A t8B t8C t8D t8E
Min 10 5 -
Typ 0 8 3-5
Max 4
Units ns ns BT BT BT
BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
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STE100P
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STE100P
PACKAGE TYPE: TQFP 64L/ BODY 10X10X1.40mm / FOOT PRINT 1.00 mm DIMENSIONS DATABOOK mm REF A A1 A2 B c D D1 D3 e E E1 E3 L L1 K
12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 3.5d 0d 7d 0.45 0.75 1.000 3.5d 1.40 0.22 0.05 1.35 0.17 0.09
DRAWING mm TYP MIN
1.420 0.100 1.400 0.200 0.065 1.360 0.175
DRAWING inch TYP MIN
.056 .004 .055 .008 .003 .054 .007
TYP
MIN
MAX
1.60 0.15 1.45 0.27 0.20
MAX
1.540 0.135 1.440 0.225 0.165
MAX
.061 .005 .057 .009 .006
12.00 10.00 7.500 0.500 12.00 10.00 7.500
11.90 9.975 7.450 0.450 11.90 9.975 7.450 0.450 0.938 1.5d
12.10 10.025 7.550 0.550 12.10 10.025 7.550
.472 .394 .295 .020 .472 .394 .295
.469 .393 .293 .018 .469 .393 .293 .018
.476 .395 .297 .022 .476 .395 .297
1.063 5.5d
.039 3.5d
.037 1.5d
.042 5.5d
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http ://www.st.com
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